The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Sep. 25, 2020
Intel Corporation, Santa Clara, CA (US);
Urusa Alaan, Hillsboro, OR (US);
Kevin L. Lin, Beaverton, OR (US);
Miriam Reshotko, Portland, OR (US);
Sarah Atanasov, Beaverton, OR (US);
Christopher Jezewski, Portland, OR (US);
Carl Naylor, Portland, OR (US);
Mauro Kobrinsky, Portland, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.