The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Sep. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sourav Dutta, Hillsboro, OR (US);

Nazila Haratipour, Portland, OR (US);

Vachan Kumar, Hillsboro, OR (US);

Uygar E. Avci, Portland, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Sou-Chi Chang, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 49/02 (2006.01); H10D 1/68 (2025.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/80 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); H10D 1/682 (2025.01); H10D 30/47 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01);
Abstract

Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.


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