The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Oct. 17, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Dongyu Fan, Wuhan, CN;

Tingting Gao, Wuhan, CN;

Wei Xie, Wuhan, CN;

Zhong Lv, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 46/00 (2026.01); H10B 80/00 (2023.01); H10P 34/42 (2026.01); H10P 54/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 46/00 (2026.01); H10B 80/00 (2023.02); H10P 34/42 (2026.01); H10P 54/00 (2026.01); H10W 90/00 (2026.01); H10W 46/503 (2026.01);
Abstract

According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.


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