The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Dec. 22, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bhaskar Jyoti Krishnatreya, Hillsboro, OR (US);

Michael J. Baker, Gilbert, AZ (US);

Feras Eid, Chandler, AZ (US);

Wenhao Li, Chandler, AZ (US);

Veronica Strong, Brussels, BE;

Thomas Sounart, Chandler, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Kimin Jun, Portland, OR (US);

Yi Shi, Chandler, AZ (US);

Xavier Brun, Chandler, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Edison Chien-an Chen, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01T 23/00 (2006.01); H10P 72/00 (2026.01); H10P 72/50 (2026.01); H10P 72/72 (2026.01);
U.S. Cl.
CPC ...
H10P 72/722 (2026.01); H10P 72/0446 (2026.01); H10P 72/50 (2026.01);
Abstract

Various aspects may provide a handling assembly. The handling assembly may include a body with a component-handling surface. The component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. The handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. In the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.


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