The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 29, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Julien Frougier, Albany, NY (US);

Sagarika Mukesh, Albany, NY (US);

Anthony I. Chou, Guilderland, NY (US);

Andrew M. Greene, Slingerlands, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Nicolas Jean Loubet, Guilderland, NY (US);

Veeraraghavan S. Basker, Fremont, CA (US);

Junli Wang, Slingerlands, NY (US);

Effendi Leobandung, Stormville, NY (US);

Jingyun Zhang, Albany, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 1/47 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H10D 1/474 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/811 (2025.01);
Abstract

A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.


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