The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Sep. 12, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sagar Suthram, Portland, OR (US);

Abhishek Sharma, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Pushkar Ranade, San Jose, CA (US);

Kuljit S. Bains, Olympia, WA (US);

Tahir Ghani, Portland, OR (US);

Anand Murthy, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
G11C 11/40626 (2013.01); H10W 90/00 (2026.01); H10W 90/288 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01);
Abstract

A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.


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