The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Jun. 29, 2022
Intel Corporation, Santa Clara, CA (US);
Sagar Suthram, Portland, OR (US);
Wilfred Gomes, Portland, OR (US);
Pushkar Sharad Ranade, San Jose, CA (US);
Ravindranath Vithal Mahajan, Chandler, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Omkar G. Karhade, Chandler, AZ (US);
Nitin A. Deshpande, Chandler, AZ (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Joshua Fryman, Corvallis, OR (US);
Stephen Morein, San Jose, CA (US);
Matthew Adiletta, Bolton, MA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.