The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Nov. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Teng Dai, New Taipei City, TW;

Chung-Ju Lee, Hsinchu City, TW;

Chih Wei Lu, Hsinchu City, TW;

Hsin-Chieh Yao, Hsinchu City, TW;

Hsi-Wen Tien, Xinfeng Township, TW;

Wei-Hao Liao, Taichung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/00 (2026.01); H10W 20/43 (2026.01); H10W 20/47 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/074 (2026.01); H10W 20/081 (2026.01); H10W 20/43 (2026.01); H10W 20/47 (2026.01);
Abstract

Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.


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