Methods for fabricating semiconductor device having nanostructure transistor with cap layer

Abstract

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.