The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Aug. 14, 2023
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Pin-Wen Chen, Keelung City, TW;
Yu-Chen Ko, Chiayi City, TW;
Chi-Yuan Chen, Hsinchu, TW;
Ya-Yi Cheng, Taichung City, TW;
Chun-I Tsai, Hsinchu, TW;
Wei-Jung Lin, Hsinchu, TW;
Chih-Wei Chang, Hsinchu, TW;
Ming-Hsing Tsai, Chu-Pei City, TW;
Syun-Ming Jang, Hsinchu, TW;
Wei-Jen Lo, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.