The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Feb. 24, 2023
International Business Machines Corporation, Armonk, NY (US);
Julien Frougier, Albany, NY (US);
Nicolas Jean Loubet, Guilderland, NY (US);
Andrew M. Greene, Slingerlands, NY (US);
Andrew Gaul, Halfmoon, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Shogo Mochizuki, Mechanicville, NY (US);
Curtis S. Durfee, Schenectady, NY (US);
Eric Miller, Albany, NY (US);
Ronald Newhart, Lebanon, PA (US);
Choudhury Mahboob Ellahi, Halfmoon, NY (US);
Anthony I. Chou, Guilderland, NY (US);
Susan Ng Emans, Albany, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.