The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jun. 15, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Wen-Yi Lin, New Taipei City, TW;

Kai-Cheng Chen, Taoyuan City, TW;

Chien-Li Kuo, Hsinchu City, TW;

Chien-Chen Li, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 74/15 (2026.01); H10W 90/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/01271 (2026.01); H10W 72/072 (2026.01); H10W 72/07211 (2026.01); H10W 72/07232 (2026.01); H10W 72/324 (2026.01); H10W 72/327 (2026.01); H10W 72/853 (2026.01); H10W 74/15 (2026.01); H10W 90/10 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

An embodiment semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region over a surface of the package substrate and the capillary underfill material may be formed over a second region of the surface of the package substrate, such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame partially surrounding the first semiconductor die and the second semiconductor die such that a multi-die chip is formed that includes the first semiconductor die, the second semiconductor die, and the multi-die frame.


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