The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Mar. 24, 2022
Intel Corporation, Santa Clara, CA (US);
Moshe Dolejsi, Portland, OR (US);
Harish Ganapathy, Portland, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Deepyanti Taneja, Happy Valley, OR (US);
Huiying Liu, Portland, OR (US);
Cheng Tan, Hillsboro, OR (US);
Timothy Jen, Portland, OR (US);
Van H. Le, Beaverton, OR (US);
Abhishek A. Sharma, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.