The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Sep. 01, 2023
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Yongjing Lin, San Jose, CA (US);

Zhihui Liu, Sunnyvale, CA (US);

Sourav Garg, Santa Clara, CA (US);

Lu Li, Santa Clara, CA (US);

Haoming Yan, Santa Clara, CA (US);

Haoyan Sha, San Jose, CA (US);

Bhaskar Jyoti Bhuyan, San Jose, CA (US);

Shih Chung Chen, Cupertino, CA (US);

Janardhan Devrajan, Santa Clara, CA (US);

Srinivas Gandikota, Santa Clara, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01); H10P 14/60 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/6735 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01); H10D 84/0167 (2025.01); H10D 84/853 (2025.01); H10D 84/854 (2025.01); H10P 14/3411 (2026.01); H10P 14/6339 (2026.01);
Abstract

Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.


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