Sourav Garg

Title: Innovations by Sourav Garg in PMOS Transistor Performance

Introduction

Sourav Garg is an accomplished inventor based in Santa Clara, CA. He has made significant contributions to the field of electronic devices, particularly in improving the performance of PMOS transistors. His innovative approaches have the potential to enhance the efficiency and reliability of various electronic applications.

Latest Patents

Sourav Garg holds a patent titled "Methods of improving PMOS transistor performance." This patent describes methods of manufacturing electronic devices, including negative metal-oxide-semiconductor (NMOS) and positive metal-oxide-semiconductor (PMOS) transistors. The patent focuses on inhibiting N-metal layer growth to improve PMOS transistor performance. It outlines two primary processes: forming a self-assembled monolayer (SAM) on the metal surface of the PMOS and creating a silicon-containing layer on the titanium nitride (TiN) surface. These methods significantly reduce or inhibit the growth of N-metal layers, such as titanium aluminum carbide (TiAlC), on the PMOS.

Career Highlights

Sourav Garg is currently employed at Applied Materials, Inc., where he continues to work on innovative solutions in the semiconductor industry. His expertise in transistor technology has positioned him as a valuable asset to his team and the company.

Collaborations

Sourav has collaborated with notable colleagues, including Yongjing Lin and Zhihui Liu. Their combined efforts contribute to advancing research and development in the field of electronic devices.

Conclusion

Sourav Garg's work in improving PMOS transistor performance showcases his innovative spirit and dedication to advancing technology. His contributions are poised to make a lasting impact on the semiconductor industry.