The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

May. 11, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hazwani Jaffar, Kepala Batas, MY;

Poh Boon Khoo, Perai, MY;

Hooi San Lam, Air Itam, MY;

Jiun Hann Sir, Gelugor, MY;

Eng Huat Goh, Penang, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 90/00 (2026.01); H10W 70/63 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/093 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 70/635 (2026.01); H10W 90/701 (2026.01);
Abstract

An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.


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