Kepala Batas, Malaysia

Hazwani Jaffar

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hazwani Jaffar. Retrieved from https://idiyas.com/inventor/hazwani-jaffar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Hazwani Jaffar: Inventor of a Molded Interconnect Memory-on-Package Design.

Introduction

Hazwani Jaffar is an inventor based in Kepala Batas, Malaysia, and is associated with Intel Corporation. His patent work includes an electronic packaging design that integrates memory with a processor system.

Latest Patents

Jaffar is credited with 1 patent: “Molded interconnect memory on package.” The invention describes an electronic system with a processor integrated circuit mounted on a first substrate and a companion component built on a second substrate. Differently positioned solder bumps connect the companion component to the first substrate, with the arrangement aligning selected bump surfaces at specified heights. The design addresses how components can be interconnected within a compact electronic package.

Career Highlights

Jaffar’s listed patent reflects work in semiconductor packaging and electronic system integration. His association with Intel Corporation places this invention within the broader field of processor and memory technologies.

Collaborations

Poh Boon Khoo and Hooi San Lam are identified as Jaffar’s coworkers. The available information does not specify their roles in the patent or whether they collaborated on this invention.

Conclusion

Hazwani Jaffar’s patent documents a packaging approach for connecting a processor and companion component through carefully arranged solder bumps, highlighting his contribution to electronic system integration.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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