The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jan. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

PO-Ting Lin, Taichung City, TW;

Yu-Ming Hsiang, New Taipei City, TW;

Wei-Chih Wen, Hsinchu County, TW;

Yin-Hao Wu, Taichung City, TW;

Wu-Wei Tsai, Taoyuan City, TW;

Hai-Ching Chen, Hsinchu City, TW;

Yu-Ming Lin, Hsinchu City, TW;

Chung-Te Lin, Tainan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/68 (2025.01); H10B 51/30 (2023.01); H10D 30/69 (2025.01); H10D 99/00 (2025.01); H10P 14/60 (2026.01); H10P 14/692 (2026.01);
U.S. Cl.
CPC ...
H10D 64/689 (2025.01); H10B 51/30 (2023.02); H10D 30/701 (2025.01); H10D 99/00 (2025.01); H10P 14/6339 (2026.01); H10P 14/69391 (2026.01); H10P 14/69397 (2026.01);
Abstract

In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.


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