The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2026
Filed:
Aug. 24, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Bok Eng Cheah, Gelugor, MY;
Jenny Shio Yin Ong, Bayan Lepas, MY;
Jackson Chung Peng Kong, Tanjung Tokong, MY;
Seok Ling Lim, Kulim Kedah, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/68 (2026.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/68 (2026.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01); H10W 72/00 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract
The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.