The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Mar. 12, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

An-Jhih Su, Taoyuan City, TW;

Chi-Hsi Wu, Hsinchu, TW;

Wen-Chih Chiou, Zhunan Township, TW;

Tsang-Jiuh Wu, Hsinchu, TW;

Der-Chyang Yeh, Hsinchu, TW;

Ming Shih Yeh, Zhubei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H10H 20/01 (2025.01); H10H 20/831 (2025.01); H10H 20/857 (2025.01); H10P 14/60 (2026.01); H10P 50/28 (2026.01); H10P 72/70 (2026.01); H10P 76/40 (2026.01); H10P 95/00 (2026.01); H10W 20/00 (2026.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10H 20/812 (2025.01); H10H 20/825 (2025.01); H10P 52/40 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10H 20/018 (2025.01); H10H 20/831 (2025.01); H10H 20/857 (2025.01); H10P 14/6334 (2026.01); H10P 14/6339 (2026.01); H10P 50/283 (2026.01); H10P 72/74 (2026.01); H10P 76/405 (2026.01); H10P 76/4085 (2026.01); H10P 95/062 (2026.01); H10W 20/033 (2026.01); H10W 20/056 (2026.01); H10W 20/062 (2026.01); H10W 20/081 (2026.01); H10W 20/092 (2026.01); H10W 20/098 (2026.01); H10W 20/43 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 72/00 (2026.01); H10W 72/012 (2026.01); H10W 72/90 (2026.01); H10W 74/016 (2026.01); H10W 74/019 (2026.01); H10W 90/00 (2026.01); H10H 20/01335 (2025.01); H10H 20/032 (2025.01); H10H 20/034 (2025.01); H10H 20/0362 (2025.01); H10H 20/0364 (2025.01); H10H 20/812 (2025.01); H10H 20/825 (2025.01); H10P 52/403 (2026.01); H10P 72/743 (2026.01); H10P 72/7432 (2026.01); H10P 72/744 (2026.01); H10W 72/01904 (2026.01); H10W 72/01935 (2026.01); H10W 72/01938 (2026.01); H10W 72/01951 (2026.01); H10W 72/07207 (2026.01); H10W 72/07236 (2026.01); H10W 80/211 (2026.01); H10W 80/312 (2026.01); H10W 80/754 (2026.01); H10W 90/794 (2026.01);
Abstract

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.


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