The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Dec. 29, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Beibei Li, Wuhan, CN;

Simin Liu, Wuhan, CN;

Wei Xu, Wuhan, CN;

Bin Yuan, Wuhan, CN;

Bo Xu, Wuhan, CN;

Yali Guo, Wuhan, CN;

Zongke Xu, Wuhan, CN;

Jiajia Wu, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Lei Xue, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/00 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02);
Abstract

A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.


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