The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
Jun. 02, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Shen-Yang Lee, Miaoli County, TW;
Hsiang-Pi Chang, New Taipei, TW;
Huang-Lin Chao, Hsinchu, TW;
Pinyen Lin, Rochester, NY (US);
TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
Gate stack fabrication techniques are disclosed for capacitance equivalent thickness scaling. An exemplary method for forming a gate stack includes forming an interfacial layer, forming a high-k dielectric layer over the interfacial layer, and forming an electrically conductive gate layer over the high-k dielectric layer. Forming the high-k dielectric layer includes forming a group 4 element-containing dielectric layer (e.g., an HfOlayer and/or a ZrOlayer) and forming a rare earth element-containing dielectric layer. In some embodiments, the rare earth element-containing dielectric layer includes yttrium and oxygen, nitrogen, carbon, or a combination thereof. The electrically conductive gate layer is formed over the rare earth element-containing dielectric layer (i.e., the rare earth element-containing dielectric layer is not removed and remains in the gate stack). The rare earth element-containing dielectric layer can be formed before, after, or between forming sublayers of group 4 element-containing dielectric layer.