The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2026
Filed:
May. 31, 2024
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Seiji Takahashi, Hsinchu, TW;
Chen-Jong Wang, Hsin-Chu, TW;
Dun-Nian Yaung, Taipei, TW;
Feng-Chi Hung, Chu-Bei, TW;
Feng-Jia Shiu, Jhudong Township, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Jhy-Jyi Sze, Hsin-Chu, TW;
Chun-Wei Chang, Tainan, TW;
Wei-Cheng Hsu, Kaohsiung, TW;
Wei Chuang Wu, Tainan, TW;
Yimin Huang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.