The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
Dec. 21, 2021
Intel Corporation, Santa Clara, CA (US);
Gerald S. Pasdast, San Jose, CA (US);
Adel A. Elsherbini, Tempe, AZ (US);
Nevine Nassif, Arlington, MA (US);
Carleton L. Molnar, Northborough, MA (US);
Vivek Kumar Rajan, Portland, OR (US);
Peipei Wang, San Jose, CA (US);
Shawna M. Liff, Scottsdale, AZ (US);
Tejpal Singh, Shrewsbury, MA (US);
Johanna M. Swan, Scottsdale, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.