The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jan. 19, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kai-Fung Chang, Hsinchu, TW;

Chin-Wei Liang, Hsinchu, TW;

Sheng-Feng Weng, Hsinchu, TW;

Ming-Yu Yen, Hsinchu, TW;

Cheyu Liu, Hsinchu, TW;

Hung-Chih Chen, Hsinchu, TW;

Yi-Yang Lei, Hsinchu, TW;

Ching-Hua Hsieh, Hsinchu, TW;

Hung-Chou Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/56 (2013.01); H01L 23/3185 (2013.01); H01L 23/49816 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/50 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81 (2013.01); H01L 2224/83 (2013.01); H01L 2224/9211 (2013.01);
Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.


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