The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2026
Filed:
Mar. 02, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
I-Ming Chang, Hsinchu, TW;
Yao-Sheng Huang, Hsinchu, TW;
Hsiang-Pi Chang, Hsinchu, TW;
Yi-Ruei Jhan, Hsinchu, TW;
Huang-Lin Chao, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01);
Abstract
A method for fabricating semiconductor devices includes forming a stack structure protruding from a substrate and including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked on top of one another. The method includes forming an isolation structure overlaying the substrate and a lower portion of the stack structure. The method includes implanting dopants into at least an upper portion of the isolation structure.