The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Aug. 19, 2022
Intel Corporation, Santa Clara, CA (US);
Adel A. Elsherbini, Chandler, AZ (US);
Shawna M. Liff, Scottsdale, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Christopher M. Pelto, Beaverton, OR (US);
Kimin Jun, Portland, OR (US);
Johanna M. Swan, Scottsdale, AZ (US);
Lei Jiang, Camas, WA (US);
Feras Eid, Chandler, AZ (US);
Krishna Vasanth Valavala, Chandler, AZ (US);
Henning Braunisch, Phoenix, AZ (US);
Patrick Morrow, Portland, OR (US);
William J. Lambert, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.