The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

May. 10, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sagar Suthram, Portland, OR (US);

Elliot Tan, Portland, OR (US);

Abhishek A. Sharma, Portland, OR (US);

Shem Odhiambo Ogadhoh, West Linn, OR (US);

Wilfred Gomes, Portland, OR (US);

Pushkar Sharad Ranade, San Jose, CA (US);

Anand S. Murthy, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H10D 84/853 (2025.01);
Abstract

IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an 'angled transistor' if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.


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