The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Mar. 25, 2022
Intel Corporation, Santa Clara, CA (US);
Tao Chu, Portland, OR (US);
Minwoo Jang, Portland, OR (US);
Aurelia Chi Wang, Hillsboro, OR (US);
Conor Puls, Portland, OR (US);
Brian Greene, Portland, OR (US);
Tofizur Rahman, Portland, OR (US);
Lin Hu, Portland, OR (US);
Jaladhi Mehta, Beaverton, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Walid Hafez, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).