logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12538470 B1

PDFFull Text
Date of Patent:
Jan. 27, 2026

Filed:

Nov. 07, 2022

Structures and methods for memory cells

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sean T. MA, Portland, OR (US);

Aaron D. Lilak, Beaverton, OR (US);

Abhishek A. Sharma, Hillsboro, OR (US);

Van H. Le, Beaverton, OR (US);

Seung Hoon Sung, Portland, OR (US);

Gilbert W. Dewey, Beaverton, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Akona IP PC

Primary Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/822 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01); H10D 1/68 (2025.01); H10D 62/10 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01); H01L 21/02 (2006.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); H01L 23/528 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 1/714 (2025.01); H10D 62/115 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01); H01L 21/0228 (2013.01); H10D 64/021 (2025.01);
Abstract

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

Find Patent Forward Citations

Loading…