The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Jan. 29, 2024
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

James Kai, Santa Clara, CA (US);

Johann Alsmeier, San Jose, CA (US);

Lito De La Rama, San Jose, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Koichi Matsuno, Fremont, CA (US);

Marika Gunji-Yoneoka, Sunnyvale, CA (US);

Makoto Koto, Yokkaichi, JP;

Hisakazu Otoi, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 62/116 (2025.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.


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