The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

May. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsung-Han Chuang, Tainan, TW;

Zhi-Chang Lin, Zhubei, TW;

Shih-Cheng Chen, New Taipei, TW;

Jung-Hung Chang, Changhua County, TW;

Chien Ning Yao, Hsinchu, TW;

Kai-Lin Chuang, Chia-Yi, TW;

Kuo-Cheng Chiang, Zhubei, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/118 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.


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