The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Mar. 30, 2022
Intel Corporation, Santa Clara, CA (US);
Deepyanti Taneja, Happy Valley, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Abhishek Anil Sharma, Portland, OR (US);
Gregory J. George, Beaverton, OR (US);
Tarannum Tiasha, Beaverton, OR (US);
Huiying Liu, Portland, OR (US);
Yue Liu, Portland, OR (US);
Moshe Dolejsi, Portland, OR (US);
Vinaykumar V. Hadagali, Portland, OR (US);
Shardul Wadekar, Hillsboro, OR (US);
Vladimir Nikitin, Portland, OR (US);
Albert B. Chen, Portland, OR (US);
Daniel J. Schinke, Portland, OR (US);
James O'Donnell, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.