The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 30, 2022
Applicant:

The Intel Corporation, Santa Clara, CA (US);

Inventors:

Yi Yang, Gilbert, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Xiaoying Guo, Chandler, AZ (US);

Jieying Kong, Chandler, AZ (US);

Ala Omer, Phoenix, AZ (US);

Christy Sennavongsa, Gilbert, AZ (US);

Wei Wei, Chandler, AZ (US);

Ao Wang, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/38 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 3/22 (2006.01); H05K 3/40 (2006.01); H01L 23/00 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 23/145 (2013.01); H01L 23/49866 (2013.01); H05K 1/115 (2013.01); H05K 3/22 (2013.01); H05K 3/4038 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H05K 1/032 (2013.01); H05K 2203/0766 (2013.01); H05K 2203/0779 (2013.01); H05K 2203/107 (2013.01);
Abstract

Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.


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