The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Aug. 08, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Lan Yao, Hubei, CN;

Lei Xue, Hubei, CN;

Ziqun Hua, Hubei, CN;

Siping Hu, Hubei, CN;

Meng Yan, Hubei, CN;

Pengan Yin, Hubei, CN;

Yucheng Zhang, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/40 (2023.01); G11C 16/04 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/40 (2023.02); G11C 16/0483 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); G11C 2213/71 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06541 (2013.01);
Abstract

The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.


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