The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jun. 17, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Cheng Chen, New Taipei, TW;

Zhi-Chang Lin, Hsinchu County, TW;

Jung-Hung Chang, Changhua County, TW;

Chien Ning Yao, Hsinchu, TW;

Tsung-Han Chuang, Tainan, TW;

Kai-Lin Chuang, Chiayi, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6713 (2025.01); H01L 21/02603 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01);
Abstract

A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.


Find Patent Forward Citations

Chen, Shih-Cheng. (2025). Method of manufacturing a semiconductor device including forming a sidewall spacer on a sidewall of a channel structure (U.S. Patent No. 12484246). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12484246

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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