The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Jul. 26, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ting-Ting Kuo, Hsinchu, TW;
Li-Hsien Huang, Hsinchu, TW;
Tien-Chung Yang, Hsinchu, TW;
Yao-Chun Chuang, Hsinchu, TW;
Yinlung Lu, Hsinchu, TW;
Jun He, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.