The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

May. 25, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Serguei Jourba, Aix en Provence, FR;

Catherine Decobert, Pourrieres, FR;

Feng Zhou, Fremont, CA (US);

Jinho Kim, Saratoga, CA (US);

Xian Liu, Sunnyvale, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/68 (2025.01); H10B 41/27 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6892 (2025.01); H10B 41/27 (2023.02); H10D 30/024 (2025.01); H10D 30/0411 (2025.01); H10D 30/6211 (2025.01); H10D 30/68 (2025.01); H10D 62/151 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.


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