The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Dec. 21, 2021
Intel Corporation, Santa Clara, CA (US);
Sanyam Bajaj, Hillsboro, OR (US);
Michael S. Beumer, Portland, OR (US);
Robert Ehlert, Portland, OR (US);
Gregory P. Mcnerney, Beaverton, OR (US);
Nicholas Minutillo, Beaverton, OR (US);
Xiaoye Qin, Beaverton, OR (US);
Johann C. Rode, Hillsboro, OR (US);
Atsunori Tanaka, Hillsboro, OR (US);
Suresh Vishwanath, Portland, OR (US);
Patrick M. Wallace, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.