The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jul. 02, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Hang Tung, Hsinchu, TW;

Tung-Liang Shao, Hsinchu, TW;

Su-Chun Yang, Hsinchu County, TW;

Geng-Ming Chang, Taichung, TW;

Chen-Hua Yu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/80 (2013.01); H01L 24/08 (2013.01); H01L 24/24 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/80004 (2013.01); H01L 2224/80143 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract

A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.


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