The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Nov. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsi-Wen Tien, Xinfeng Township, TW;

Wei-Hao Liao, Taichung, TW;

Yu-Teng Dai, New Taipei, TW;

Hsin-Chieh Yao, Hsinchu, TW;

Chih Wei Lu, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01);
Abstract

The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.


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