The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Jul. 08, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chin-Hua Wang, New Taipei, TW;
Chia Kuei Hsu, Hsinchu, TW;
Shu-Shen Yeh, Taoyuan, TW;
Po-Chen Lai, Hsinchu County, TW;
Po-Yao Lin, Zhudong Township, Hsinchu County, TW;
Shin-Puu Jeng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.