The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2025
Filed:
Aug. 17, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Kai-Fung Chang, Taipei, TW;
Sheng-Feng Weng, Taichung, TW;
Ming-Yu Yen, MiaoLi County, TW;
Wei-Jhan Tsai, Kaohsiung, TW;
Chao-Wei Chiu, Hsinchu, TW;
Chao-Wei Li, Hsinchu, TW;
Chih-Wei Lin, Hsinchu County, TW;
Ching-Hua Hsieh, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.