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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12354910 B1

PDFFull Text
Date of Patent:
Jul. 08, 2025

Filed:

Nov. 13, 2023

Bi-layer alloy liner for interconnect metallization and methods of forming the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Huei-Wen Hsieh, Hsinchu, TW;

Kai-Shiang Kuo, Hsinchu, TW;

Cheng-Hui Weng, Hsinchu, TW;

Chun-Sheng Chen, Hsinchu, TW;

Wen-Hsuan Chen, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Nicholas J Tobergte

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76882 (2013.01); H01L 21/7684 (2013.01); H01L 21/76846 (2013.01); H01L 21/76858 (2013.01); H01L 21/76862 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 21/76807 (2013.01); H01L 21/76849 (2013.01); H01L 21/76883 (2013.01); H01L 2221/1073 (2013.01); H10D 84/834 (2025.01);
Abstract

A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

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