The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

May. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsin-Chieh Yao, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Chih Wei Lu, Hsinchu, TW;

Hsi-Wen Tien, Xinfeng Township, TW;

Yu-Teng Dai, New Taipei, TW;

Wei-Hao Liao, Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01);
Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.


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