The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jul. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsin-Yen Huang, New Taipei, TW;

Shao-Kuan Lee, Hsinchu, TW;

Cheng-Chin Lee, Hsinchu, TW;

Hsiang-Wei Liu, Tainan, TW;

Tai-I Yang, Hsinchu, TW;

Chia-Tien Wu, Taichung, TW;

Hai-Ching Chen, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2005.12); H01L 21/768 (2005.12); H01L 23/528 (2005.12); H01L 29/45 (2005.12);
U.S. Cl.
CPC ...
H01L 21/76885 (2012.12); H01L 21/76829 (2012.12); H01L 21/76834 (2012.12); H01L 21/76837 (2012.12); H01L 21/7684 (2012.12); H01L 21/76886 (2012.12); H01L 23/528 (2012.12); H01L 29/45 (2012.12);
Abstract

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.


Find Patent Forward Citations

Loading…