The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

May. 12, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Chen-Ming Huang, Tainan, TW;

Wen-Tuo Huang, Tainan, TW;

Yu-Hsiang Yang, Tainan, TW;

Yu-Ling Hsu, Tainan, TW;

Wei-Lin Chang, Changhua, TW;

Chia-Sheng Lin, Tainan, TW;

ShihKuang Yang, Tainan, TW;

Yu-Chun Chang, Tainan, TW;

Hung-Ling Shih, Tainan, TW;

Po-Wei Liu, Tainan, TW;

Shih-Hsien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2005.12); G11C 16/10 (2005.12); H01L 29/66 (2005.12); H01L 29/78 (2005.12); H10B 41/35 (2022.12);
U.S. Cl.
CPC ...
G11C 16/10 (2012.12); H01L 29/6656 (2012.12); H01L 29/7841 (2012.12); H10B 41/35 (2023.01); G11C 16/04 (2012.12);
Abstract

A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.


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