The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Jan. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsi-Wen Tien, Xinfeng Township, TW;

Wei-Hao Liao, Taichung, TW;

Yu-Teng Dai, New Taipei, TW;

Hsin-Chieh Yao, Hsinchu, TW;

Chih-Wei Lu, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/76834 (2013.01); H01L 21/7684 (2013.01); H01L 21/76885 (2013.01);
Abstract

In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.


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