The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Jan. 31, 2023
Intel Corporation, Santa Clara, CA (US);
Abhishek A. Sharma, Portland, OR (US);
Juan G. Alzate-Vinasco, Tigard, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Pei-hua Wang, Beaverton, OR (US);
Van H. Le, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Umut Arslan, Portland, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Chieh-jen Ku, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.