The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Sep. 27, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company Limited, Nanjing, CN;

Tsmc China Company Limited, Shanghai, CN;

Inventors:

Xiu-Li Yang, Shanghai, CN;

He-Zhou Wan, Shanghai, CN;

Mu-Yang Ye, Nanjing, CN;

Lu-Ping Kong, Nanjing, CN;

Ming-Hung Chang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 2207/12 (2013.01);
Abstract

A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.


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